This invention relates to an FM detector, and more particularly to an FM detector which employs an analog multiplier and a phase shift network.
FM detectors employing analog multipliers and phase shift networks have been known from "1968 INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS", pp. 116-117; "IEEE JOURNAL OF SOLID-STATE CIRCUITS", VOL. SC-3, No. 4, December 1968, pp. 373-380; etc.
In the FM detectors of this type, an FM input signal and a signal which is provided from the phase shift network and which has a phase deviation proportional to the frequency of the FM input signal are applied to the analog multiplier.
The known FM detector is put into the form of a semiconductor integrated circuit, and has its circuits directly coupled. Demodulated signals are derived from the collectors of a plurality of transistors which constitute the multiplier and whose bases and emitters are respectively connected in common.
With the circuit arrangement, even when the delay times of the individual transistors have fluctuated in dependence on the FM signal level, the output signals of these transistors are not influenced by the fluctuations in the delay times because the transistors execute substantially the same operations. As a result, the phases of the output signals of the FM detector are not subject to any evil effect attributed to the variation of the FM input signal level.
According to the inventors' study, however, it has been revealed that with the known FM detector, the signal-to-noise ratio of a detected output signal obtained is comparatively low.